Until now I’ve experimenting with a Lab, clock generator to be able to control the “Duty Cycle” I also thought this could have some part on the problem so I’ve tested with several “duty cycles”, but from you explanation it all points now to the way I’m reading the IOs and when they are realy sampled.
Also if I’m using the “LogicLab watches functionality” to look at counter value during runtime do this impact on the PLC execution time in a way that it could also lead to the problems I’m having now ?
I’m going to test the project you have posted and will post back the results.